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Daniel Sorin

Professor

Duke University · United States
Computer architectureimproving computer system fault tolerancedeveloping memory systems for multicore processorsand designing special-purpose accelerators

About

Dr. Daniel Sorin is a professor of Electrical and Computer Engineering at Duke University. His research interests are primarily in computer architecture and dependability.

Education

  • B.S. Duke University, 1996
  • M.S. University of Wisconsin, Madison, 1998
  • Ph.D. University of Wisconsin, Madison, 2002
  • Professor of Electrical and Computer Engineering
  • Bass Fellow
  • Associate Chair of Education in the Department of Electrical and Computer Engineering
  • Professor in Computer Science

Selected publications

  • Zhang AQ, Goens A, Sorin D, Nagarajan V. A Formally Verified Foundation for Compositional Heterogeneous Coherence. Proceedings of the ACM on Programming Languages. 2026 Jun 1;10.
  • Sorin DJ, Nagarajan V. Message from the Program Chairs. Proceedings International Symposium on Computer Architecture. 2025 Jun 21;XVIIu2013XVIII.
  • Srivastava S, Rydell F, Goens A, Nagarajan V, Sorin DJ. Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology. IEEE Computer Architecture Letters. 2025 Jan 1;24(2):305u20138.
  • Li W, Goens A, Oswald N, Nagarajan V, Sorin DJ. Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. In: Proceedings International Symposium on Computer Architecture. 2024. p. 182u201397.
  • Zhang AQ, Goens A, Oswald N, Grosser T, Sorin D, Nagarajan V. PipeGen: Automated Transformation of a Single-Core Pipeline Into a Multicore Pipeline for a Given Memory Consistency Model. In: Parallel Architectures and Compilation Techniques Conference Proceedings Pact. 2024. p. 1u201313.
  • Mazurek F, Tschand A, Wang Y, Pajic M, Sorin D. Rigorous Evaluation of Computer Processors with Statistical Model Checking. In: Proceedings of the 56th Annual IEEE ACM International Symposium on Microarchitecture Micro 2023. 2023. p. 1242u201354.
  • Oswald N, Nagarajan V, Sorin DJ, Gavrielatos V, Olausson TX, Carr R. HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. IEEE Micro. 2023 Jul 1;43(4):62u201370.
  • Oswald N, Nagarajan V, Sorin DJ, Gavrielatos V, Olausson T, Carr R. HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. In: Proceedings International Symposium on High Performance Computer Architecture. 2022. p. 756u201371.
  • Mehrabi A, Sorin DJ, Lee BC. Spatiotemporal Strategies for Long-Term FPGA Resource Management. In: Proceedings 2022 IEEE International Symposium on Performance Analysis of Systems and Software Ispass 2022. 2022. p. 198u2013209.
  • Sorin DJ. Reconfigurable Hardware in Postsilicon Microarchitecture. Computer. 2021 Mar 1;54(3):4u20135.

Data verified 9/6/2026Source

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