Snorre Aunet

About

We present a power and area-efficient solution for robust asynchronous sampling of a ripple counter for coarse-fine VCO-ADCs. We show that by replacing the parallel register with a delay-matched sequential register and utilizing asynchronous arbitration, sampling errors are avoided. Post-layout simulation of a 7-bit system shows that our proposed solution tolerates VCO frequencies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$197\times $ </tex-math></inline-formula> higher than the baseline design, while requiring a 42 % increase in power and a 26 % area overhead, thereby improving upon a state-of-the-art double-counter solution.

Selected publications

• Scientific articles and book chapters
• Khalid, Muhammad Umer; Ytterdal, Trond & Aunet, Snorre (2026). A Sub-70-mV SRAM Based on DTMOS Schmitt-Trigger Circuits in 130-nm SOI CMOS for Self-Powered IoT. IEEE Access. 14, p. 113511–113530. doi: 10.1109/ACCESS.2026.3715921. Full text in Research Archive
• Su, Shengkai & Aunet, Snorre (2026). Self-Oscillating Joule Thief Converters for MEMS Electromagnetic Energy Harvesting: Analytical Modeling and Experimental Validation. IEEE transactions on industrial electronics (1982. Print). ISSN 0278-0046. doi: 10.1109/TIE.2026.3663767. Full text in Research Archive
• Moulin, Kaspar Sigurd; Lande, Tor Sverre; Aunet, Snorre & Wisland, Dag Trygve Eckhoff (2026). Efficient Asynchronous Sampling of Ripple Counter in VCO-ADC Using Ripple Register and Event Arbitration. IEEE Transactions on Circuits and Systems - II - Express Briefs. ISSN 1549-7747. 73(2), p. 138–142. doi: https:/ieeexplore.ieee.org/document/11339947. Full text in Research Archive Show summary We present a power and area-efficient solution for robust asynchronous sampling of a ripple counter for coarse-fine VCO-ADCs. We show that by replacing the parallel register with a delay-matched sequential register and utilizing asynchronous arbitration, sampling errors are avoided. Post-layout simulation of a 7-bit system shows that our proposed solution tolerates VCO frequencies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$197\times $ </tex-math></inline-formula> higher than the baseline design, while requiring a 42 % increase in power and a 26 % area overhead, thereby improving upon a state-of-the-art double-counter solution.
• Roland, Markus Heyerdahl; Aunet, Snorre & Yakovlev, Alexandre (2025). Faster Training of Tsetlin Machines With Deterministic Multi-Step Automata. In Lei, Jiao & Shafik, Rishad Ahmed (Ed.), Tsetlin Machine (ISTM), International Symposium on the. IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331569228. p. 48–55. doi: 10.1109/ISTM67926.2025.00016. Full text in Research Archive Show summary This article investigates the use of "multi-step variable structure finite-state" automata (MVFA) in place of Tsetlin automata (TA) for a software implementation of the coalesced Tsetlin machine (CoTM) with up to 2048 clauses for classification of the MNIST dataset. The use of deterministic MVFA compared to TA resulted in a harmonic mean speedup of 5.6 times for training time per epoch and a mean increase in accuracy of 0.23% over the last 10 out of 50 epochs of training for the model sizes investigated. For CoTM with 1024 clauses, it was here observed that TA requires a minimum of 7 bits of state to obtain maximal first epoch accuracy, while MVFA requires a minimum of 10–12 bits. In light of previous work on MVFA, the findings presented here points to that the optimal choice of stochastic vs. deterministic automata depends on characteristics of the dataset.
• Nägle, Louisa Charlotte; Aunet, Snorre & Rückert, Ulrich (2025). Exploiting Multi-VT FDSOI Technology for Improved Area and Energy Trade-Offs for Ultra-Low Voltage Schmitt Triggers. In Nurmi, Jari; Aunet, Snorre & Saberkari, Alireza (Ed.), 2025 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331515010. p. 1–7. doi: 10.1109/NorCAS66540.2025.11231312. Full text in Research Archive Show summary This work presents the design and comparison of three Schmitt Trigger inverter implementations, optimized for ultra-low-voltage operation down towards 100mV, targeting energy-constrained applications such as IoT sensor nodes and biomedical interfaces. The commercial 22nm FD-SOI (22FDX) process by GlobalFoundries is used. The impact of transistor threshold voltage type selection and sizing on performance, energy efficiency, and layout area is investigated. Device characteristics of NMOS and PMOS variants were analyzed to enable combinations with decreased area. The inverters were evaluated using DC analysis and as ring oscillators in transient analysis to extract propagation delay, power, and energy down to 100mV. The results demonstrate that carefully pairing low- and regular threshold devices (multi-VT) allows for favorable tradeoffs between speed and leakage, with minimum energy points occurring in the subthreshold region. With approximately twice the propagation delay and one-eighth the power consumption, the energy and total area are approximately four times less than those of the reference Schmitt Trigger inverter. Their robust functionality at ultra-low supply voltages makes them promising building blocks for future subthreshold and energy-harvesting systems.
• Khalid, Muhammad Umer; Ytterdal, Trond & Aunet, Snorre (2025). Comparative Analysis of Full Adders Based on DTMOS Schmitt-Trigger Standard Cells Operating at Sub-100 mV Supply Voltage. In editors, IEEE (Eds.), 2025 40th Conference on Design of Circuits and Integrated Systems (DCIS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331580919. p. 182–187. doi: 10.1109/dcis67520.2025.11281931. Full text in Research Archive
• Khalid, Muhammad Umer; Ytterdal, Trond & Aunet, Snorre (2025). Robust DTMOS Schmitt-Trigger Circuits in 130 nm SOI CMOS for Sub-100mV Supply Voltage. In editors, IEEE (Eds.), 2025 40th Conference on Design of Circuits and Integrated Systems (DCIS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331580919. doi: 10.1109/dcis67520.2025.11281895. Full text in Research Archive